Friday, December 29, 2006
Check Yahoo ID online / offline
Introduction...
Are you using Yahoo Messenger or Skype? If so, you can find which user/friend from your list is truly online or hiding from you, beeing invisible. Check-Yahoo Check-ID presents for the first time a simple solution to find out who's online and who's hiding. You may also find easily its IP if you read the manual from the page: Get-Ip. The page is friendly, with an interface made also for unexperinced people. Soon you could find out many infos about a YMSG yahoo messenger or skype, such as: If you are in a chat session with an webcam or just voice, if you are in a chat-room, etc?
What's its is use ?
Go spy people on your list. Check if they are online or logged in or Offline. If they are Online you can check if their status is on Visible or on Invisible. Use their yahoo id or the ip from where they use to log in. Also you've got a link where you can find out how u can trace an IP not only for Yahoo users but also for the ones from other networks like MSN, ICQ, SKYPE or mIRC, the method for finding their IP beeing alike with a difference in forecasting data. For this you must read carefully the help from the page: Get-Ip. CheckYahoo will show you the real online status of your Yahoo! Messenger users. You can regularly check to see if they are online, even if they are invisible or are using Stealth Mode. Is easy and siple not advanced experience. Is 100% secure becouse never need your password ID. You could use your regular Yahoo! Messenger account for this, but for 100% real status use IP Check. Ip Check is working 100% if: user have Real IP and no firewall or router port filters.
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Wednesday, December 27, 2006
Filme de Sarbatori ( Torrents Movie)
Sunt trecute numele fisierelor torrent la cele mai noi versiuni pentru care exista si subtitrari pe internet! Vizionare placuta!
-----------------------
A.Good.Year.TS.XViD-maVenssupplieR
Abominable.2006.LiMiTED.DVDSCR.XviD-XanaX
Air.Buddies[2006]DvDrip[Eng]-aXXo
American.Pie.5.2006.UNRATED.DVDRip.XviD-VoMiT
Babel.DVDSCR.XViD-HLS
Bon.Cop.Bad.Cop.2006.LIMITED.DVDRip.XviD-MESS
Children.Of.Men.DVD.SCREENER.XViD-PUKKA
Danika.2006.DVDRip.XviD-VoMiT
Driving.Lessons.LiMiTED.DVDRip.XviD-DoNE
Eragon.TS.XViD-PUKKA
Even.Money.2006.DVDSCR.XViD-TDL_[www.NewTorrents.info]
Fatal.Contact.2006.DVDRip.XviD-ESPiSE
Flushed.Away.DVDSCR.XviD-iMBT.3582367.TPB
Happy.Feet.2006.TS.XviD-XanaX
Invincible.DVDRip.XviD-DiAMOND_
Little.Miss.Sunshine.DVDRip.XviD-DiAMOND
Lady.In.The.Water[2006]DvDrip[Eng]-aXXo
Lonely.Hearts.FS.DVDSCR.XviD_ASTEROiDS
Man.Of.The.Year.R5.XViD-PUKKA
Open.Season.R5.XViD-XanaX
Rob-B-Hood.2006.DVDRip.XviD-ESPiSE
Severance.2006.LiMiTED.DVDRiP.XViD-TDL
Step.Up[2006]DvDrip[Eng]-aXXo
Stormbreaker[2006]DvDrip[Eng]-aXXo
The.Architect.LiMiTED.DVDSCR.XviD-HLS.3565670.TPB
The.Black.Dahlia.DVDRip.XviD-DiAMOND
The.Celestine.Prophecy.LIMITED.DVDRip.XviD-DMT
The.Departed.DVDRiP.XViD_DvF_
The.Fountain.TS.XViD_[Sonic].3573787.TPB
The.Last.Kiss.DVDRip.XviD-DiAMOND
The.Night.Listener.DVDRip.XviD-DiAMOND
The.Road.To.Guantanamo[2006]DvDrip.AC3[Eng]-aXXo
The.Santa.Clause.3.REPACK.TELESYNC.XviD-ORC
The.Visitation.2006.DVDRip.XviD-CHWDF
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Tuesday, December 26, 2006
Even Money, American Pie V - The Naked Mile, Children of Men!
Filme de revelion!
Even Money, American Pie V - The Naked Mile, Children of Men etc...
Even Money !
- Kim Basinger
- Danny DeVito
- Ray Liotta
- Forest Whitaker
- Carla Gugino
Un film cu o intrebare subtila ... ce dorim de la viata ?
.....
"Daca vrei sa stii adevarul despre cineva, gaseste'te visele si da'le inapoi. Cu totii urmarim ceva... sau mai bine spus banii! Sau dragostea ? Poate ca inca o sansa ? ... Ceea ce cautam cu adevarat e mai multa viata, mai mult din viata aceasta minunata. Dar daca nu ai grija o sa cauti si mai mult si o sa ajungi sa ai si mai putin!"
pe scurt: Symply Too Good To Be True !!! ca sa intelegeti trebuie sa'l vedeti.
"Nu trebuie sa risti ceea ce nu'ti poti permite sa pierzi! Poate crezi ca esti diferit... dar intr'o buna zi tu o sa'ti doresti mai mult, intrebare este:
Pe ce esti dispus sa mizezi."
=================
American Pie V - The Naked Mile.
Prima impresie dupa primul minut ... Deja Vu si Incitat, comic... merita vazut !
Primele impresii dupa sfarsitul filmului:
- Un scenarist ce iubeste virginitatea la barbati,
- seamana ce si ce cu "American Pie" dar nu rasare
- alti actori, slabuti fata de cei din seriile anterioare !
- multa lume dezbracata ... wink.gif
- sex... dezmat... ca'n filme!
----------
Daca nu ai ce face merita sa'ti pierzi timpul cu el !
=================
Children of Men!
Super film... putin cam dramatic finalul, dar merita atentia!
Cred ca a fost filmat in Romania, daca nu tot, cel putin o parte sigur !
Wtf... nu am mai scos o lacrima de ceva vreme... nu am reusit sa ma abtin la faza cand totul se opreste, nimeni nu mai trage ... scancetul unui copil ia inmarmurit pe toti...
sad.gif NO CHILDREN. NO FUTURE. NO HOPE !!! TRUE!
-----------
Pe masura ce le vad o sa mai scriu cate ceva despre ele...
Sarbatori fericite!
Bloggers , Technorati claim
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Sunday, December 24, 2006
forum about: livejasmine, adultvideochat, needlive, livejasmin, adult video chat, videochat si multe altele
This summary is not available. Please
click here to view the post.
Saturday, December 23, 2006
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Amd MultiCore, Intel MultiCore V
AMD Multicore and Intel Multicore
----------------------------
Parallel computing
Parallel computing is the simultaneous execution of the same task (split up and specially adapted) on multiple processors in order to obtain results faster. The idea is based on the fact that the process of solving a problem usually can be divided into smaller tasks, which may be carried out simultaneously with some coordination.
Parallel computing systems
A parallel computing system is a computer with more than one processor for parallel processing. In the past, each processor of a multiprocessing system always came in its own processor packaging, but recently introduced multicore processors contain multiple logical processors in a single package.
There are many different kinds of parallel computers. They are distinguished by the kind of interconnection between processors (known as "processing elements" or PEs) and memory.
Flynn's taxonomy, one of the most accepted taxonomies of parallel architectures, classifies parallel (and serial) computers according to
* whether all processors execute the same instructions at the same time (single instruction/multiple data -- SIMD) or
* each processor executes different instructions (multiple instruction/multiple data -- MIMD).
One major way to classify parallel computers is based on their memory architectures. Shared memory parallel computers have multiple processors accessing all available memory as global address space. They can be further divided into two main classes based on memory access times: Uniform memory access (UMA), in which access times to all parts of memory are equal, or Non-Uniform memory access (NUMA), in which they are not. Distributed memory parallel computers also have multiple processors, but each of the processors can only access its own local memory; no global memory address space exists across them.
Parallel computing systems can also be categorized by the numbers of processors in them. Systems with thousands of such processors are known as massively parallel. Subsequently there are what are referred to as "Large scale" vs "Small scale" parallel processors. This depends on the size of the processor, eg. a PC based parallel system would generally be considered a small scale system.
Parallel processor machines are also divided into symmetric and asymmetric multiprocessors, depending on whether all the processors are the same or not (for instance if only one is capable of running the operating system code and others are less privileged).
A variety of architectures have been developed for parallel processing. For example a Ring architecture has processors linked by a ring structure. Other architectures include Hypercubes, Fat trees, systolic arrays, and so on.
Theory and practice
Parallel computers can be modelled as Parallel Random Access Machines (PRAMs). The PRAM model ignores the cost of interconnection between the constituent computing units, but is nevertheless very useful in providing upper bounds on the parallel solvability of many problems. In reality the interconnection plays a significant role.
The processors may communicate and cooperate in solving a problem or they may run independently, often under the control of another processor which distributes work to and collects results from them (a "processor farm").
Processors in a parallel computer may communicate with each other in a number of ways, including shared (either multiported or multiplexed) memory, a crossbar, a shared bus or an interconnect network of a myriad of topologies including star, ring, tree, hypercube, fat hypercube (a hypercube with more than one processor at a node), an n-dimensional mesh, etc. Parallel computers based on interconnect network need to employ some kind of routing to enable passing of messages between nodes that are not directly connected. The communication medium used for communication between the processors is likely to be hierarchical in large multiprocessor machines. Similarly, memory may be either private to the processor, shared between a number of processors, or globally shared. Systolic array is an example of a multiprocessor with fixed function nodes, local-only memory and no message routing.
Approaches to parallel computers include:
* Multiprocessing
* Computer cluster
* Parallel supercomputers
* Distributed computing
* NUMA vs. SMP vs. massively parallel computer systems
* Grid computing
Performance vs. cost
While a system of n parallel processors is less efficient than one n-times-faster processor, the parallel system is often cheaper to build. Parallel computation is used for tasks which require very large amounts of computation, take a lot of time, and can be divided into n independent subtasks. In recent years, most high performance computing systems, also known as supercomputers, have parallel architectures.
Terminology in parallel computing
Some frequently used terms in parallel computing are:
Task
a logically high level, discrete, independent section of computational work. A task is typically executed by a processor as a program
Synchronization
the coordination of simultaneous tasks to ensure correctness and avoid unexpected race conditions.
Speedup
also called parallel speedup, which is defined as wall-clock time of best serial execution divided by wall-clock time of parallel execution.
Parallel overhead
the extra work associated with parallel version compared to its sequential code, mostly the extra CPU time and memory space requirements from synchronization, data communications, parallel environment creation and cancellation, etc.
Scalability
a parallel system's ability to gain proportionate increase in parallel speedup with the addition of more processors.
Algorithms
Parallel algorithms can be constructed by redesigning serial algorithms to make effective use of parallel hardware. However, not all algorithms can be parallelized. This is summed up in a famous saying:
One woman can have a baby in nine months, but nine women can't have a baby in one month.
In practice, linear speedup (i.e., speedup proportional to the number of processors) is very difficult to achieve. This is because many algorithms are essentially sequential in nature (Amdahl's law states this more formally).
Certain workloads can benefit from pipeline parallelism when extra processors are added. This uses a factory assembly line approach to divide the work. If the work can be divided into n stages where a discrete deliverable is passed from stage to stage, then up to n processors can be used. However, the slowest stage will hold up the other stages so it is rare to be able to fully use n processors.
Parallel programming
Parallel programming is the design, implementation, and tuning of parallel computer programs which take advantage of parallel computing systems. It also refers to the application of parallel programming methods to existing serial programs (parallelization).
Parallel programming focuses on partitioning the overall problem into separate tasks, allocating tasks to processors and synchronizing the tasks to get meaningful results. Parallel programming can only be applied to problems that are inherently parallelizable, mostly without data dependence. A problem can be partitioned based on domain decomposition or functional decomposition, or a combination.
There are two major approaches to parallel programming.
* implicit parallelism -- the system (the compiler or some other program) partitions the problem and allocates tasks to processors automatically (also called automatic parallelizing compilers) -- or
* explicit parallelism where the programmer must annotate their program to show how it is to be partitioned.
Many factors and techniques impact the performance of parallel programming:
* Load balancing attempts to keep all processors busy by moving tasks from heavily loaded processors to less loaded ones.
Some people consider parallel programming to be synonymous with concurrent programming. Others draw a distinction between parallel programming, which uses well-defined and structured patterns of communications between processes and focuses on parallel execution of processes to enhance throughput, and concurrent programming, which typically involves defining new patterns of communication between processes that may have been made concurrent for reasons other than performance. In either case, communication between processes is performed either via shared memory or with message passing, either of which may be implemented in terms of the other.
Programs which work correctly in a single CPU system may not do so in a parallel environment. This is because multiple copies of the same program may interfere with each other, for instance by accessing the same memory location at the same time. Therefore, careful programming (synchronization) is required in a parallel system.
Parallel programming models
Main article: Parallel programming model
A parallel programming model is a set of software technologies to express parallel algorithms and match applications with the underlying parallel systems. It encloses the areas of applications, languages, compilers, libraries, communication systems, and parallel I/O. People have to choose a proper parallel programming model or a form of mixture of them to develop their parallel applications on a particular platform.
Parallel models are implemented in several ways: as libraries invoked from traditional sequential languages, as language extensions, or complete new execution models. They are also roughly categorized for two kinds of systems: shared memory systems and distributed memory systems, though the lines between them are largely blurred nowadays.
Topics in parallel computing
Generic:
* Automatic parallelization
* Parallel algorithm
* Cellular automaton
* Grand Challenge problems
Computer science topics:
* Lazy evaluation vs strict evaluation
* Complexity class NC
* Communicating sequential processes
* Dataflow architecture
* Parallel graph reduction
Practical problems:
* Parallel computer interconnects
* Parallel computer I/O
* Reliability problems in large systems
Programming languages/models:
* OpenMP
* Message Passing Interface/MPICH
* Occam
* Linda
* Cilk
Specific:
* Atari Transputer Workstation
* BBN Butterfly computers
* Beowulf cluster
* Blue Gene
* Deep Blue
* Fifth generation computer systems project
* ILLIAC III
* ILLIAC IV
* Parallel Element Processing Ensemble
* Meiko Computing Surface
* NCUBE
* Teramac
* Transputer
Parallel computing to increase fault tolerance:
* Master-checker
Companies (largely historical):
* Thinking Machines
* Convex Computer Corporation
* Meiko
* Control Data Corporation
* Myrias Research Corporation
======================
Source: http://en.wikipedia.org/wiki/Parallel_computing
======================
Amd MultiCore, Intel MultiCore II
AMD Multicore and Intel Multicore
----------------------------
Multiprocessing
From Wikipedia, the free encyclopedia
Jump to: navigation, search
Multiprocessing is a generic term for the use of two or more central processing units (CPUs) within a single computer system. There are many variations on this basic theme, and the definition of multiprocessing can vary with context, mostly as a function of how CPUs are defined (multiple cores on one die, multiple chips in one package, multiple packages in one system unit, etc.).
Multiprocessing sometimes refers to the execution of multiple concurrent software processes in a system as opposed to a single process at any one instant. However, the term multiprogramming is more appropriate to describe this concept, which is implemented mostly in software, whereas multiprocessing is more appropriate to describe the use of multiple hardware CPUs. A system can be both multiprocessing and multiprogramming, only one of the two, or neither of the two.
Processor symmetry
In a multiprocessing system, all CPUs may be equal, or some may be reserved for special purposes. A combination of hardware and operating-system software design considerations determine the symmetry (or lack thereof) in a given system. For example, hardware or software considerations may require that only one CPU respond to all hardware interrupts, whereas all other work in the system may be distributed equally among CPUs; or execution of kernel-mode code may be restricted to only one processor (either a specific processor, or only one processor at a time), whereas user-mode code may be executed in any combination of processors. Multiprocessing systems are often easier to design if such restrictions are imposed, but they tend to be less efficient than systems in which all CPUs are utilized equally.
Systems that treat all CPUs equally are called symmetric multiprocessing (SMP) systems. In systems where all CPUs are not equal, system resources may be divided in a number of ways, including asymmetric multiprocessing (ASMP), non-uniform memory access (NUMA) multiprocessing, and clustered multiprocessing (qq.v.).
Instruction and data streams
In multiprocessing, multiple processors can be used within a single system to execute multiple, independent sequences of instructions in multiple contexts (multiple-instruction, multiple-data or MIMD); a single sequence of instructions in multiple contexts (single-instruction, multiple-data or SIMD, often used in vector processing); and multiple sequences of instructions in a single context (multiple-instruction, single-data or MISD, used for redundancy in fail-safe systems and sometimes applied to describe pipelined processors or hyperthreading).
Processor coupling
Tightly-coupled multiprocessor systems contain multiple CPUs that are connected at the bus level. These CPUs may have access to a central shared memory (SMP or UMA), or may participate in a memory hierarchy with both local and shared memory (NUMA). The IBM p690 Regatta is an example of a high end SMP system. Chip multiprocessors, also known as multi-core computing, involves more than one processor placed on a single chip and can be thought of the most extreme form of tightly-coupled multiprocessing. Mainframe systems with multiple processors are often tightly-coupled.
Loosely-coupled multiprocessor systems (often referred to as clusters) are based on multiple standalone single or dual processor commodity computers interconnected via a high speed communication system (Gigabit Ethernet is common). A Linux Beowulf cluster is an example of a loosely-coupled system.
Tightly-coupled systems perform better and are physically smaller than loosely-coupled systems, but have historically required greater initial investments and may depreciate rapidly; nodes in a loosely-coupled system are usually inexpensive commodity computers and can be recycled as independent machines upon retirement from the cluster.
Power consumption is also a consideration. Tightly-coupled systems tend to be much more energy efficient than clusters. This is due to fact that considerable economies can be realized by designing components to work together from the beginning in tightly-coupled systems, whereas loosely-coupled systems use components that were not necessarily intended specifically for use in such systems.
MIMD multiprocessing
MIMD multiprocessing architecture is suitable for a wide variety of tasks in which completely independent and parallel execution of instructions touching different sets of data can be put to productive use. For this reason, and because it is easy to implement, MIMD predominates in multiprocessing.
Processing is divided into multiple threads, each with its own hardware processor state, within a single software-defined process or within multiple processes. Insofar as a system has multiple threads awaiting dispatch (either system or user threads), this architecture makes good use of hardware resources.
MIMD does raise issues of deadlock and resource contention, however, since threads may collide in their access to resources in an unpredictable way that is difficult to manage efficiently. MIMD requires special coding in the operating system of a computer but does not require application changes unless the applications themselves use multiple threads (MIMD is transparent to single-threaded applications under most operating systems, if the applications do not voluntarily relinquish control to the OS). Both system and user software may need to use software constructs such as semaphores (also called locks or gates) to prevent one thread from interfering with another if they should happen to cross paths in referencing the same data. This gating or locking process increases code complexity, lowers performance, and greatly increases the amount of testing required, although not usually enough to negate the advantages of multiprocessing.
Similar conflicts can arise at the hardware level between CPUs (cache contention and corruption, for example), and must usually be resolved in hardware, or with a combination of software and hardware (e.g., cache-clear instructions).
SIMD multiprocessing
SIMD multiprocessing is well suited to parallel or vector processing, in which a very large set of data can be divided into parts that are individually subjected to identical but independent operations. A single instruction stream directs the operation of multiple processing units to perform the same manipulations simultaneously on potentially large amounts of data.
For certain types of computing applications, this type of architecture can produce enormous increases in performance, in terms of the elapsed time required to complete a given task. However, a drawback to this architecture is that a large part of the system falls idle when applications or system tasks are executed that cannot be divided into units that can be processed in parallel.
Additionally, applications must be carefully and specially written to take maximium advantage of the architecture, and often special optimizing compilers designed to produce code specifically for this environment must be used. Some compilers in this category provide special constructs or extensions to allow programmers to directly specify operations to be performed in parallel (e.g., DO FOR ALL statements in the version of FORTRAN used on the ILLIAC IV, which was a SIMD multiprocessing supercomputer).
SIMD multiprocessing finds wide use in certain domains such as computer simulation, but is of little use in general-purpose desktop and business computing environments.
MISD multiprocessing
MISD multiprocessing offers mainly the advantage of redundancy, since multiple processing units perform the same tasks on the same data, reducing the chances of incorrect results if one of the units fails. MISD architectures may involve comparisons between processing units to detect failures. Apart from the redundant and fail-safe character of this type of multiprocessing, it has few advantages, and it is very expensive. It does not improve performance. It can be implemented in a way that is transparent to software.
====================
Source: http://en.wikipedia.org/wiki/Multiprocessing
====================
Amd MultiCore, Intel MultiCore II
AMD Multicore and Intel Multicore
----------------------------
Hyper-threading
Hyper-threading, officially called Hyper-Threading Technology (HTT), is Intel's trademark for their implementation of the simultaneous multithreading technology on the Pentium 4 microarchitecture. It is a more advanced form of Super-threading that debuted on the Intel Xeon processors and was later added to Pentium 4 processors. The technology improves processor performance under certain workloads by providing useful work for execution units that would otherwise be idle, for example during a cache miss. A Pentium 4 with Hyper-Threading enabled is treated by the operating system as two processors instead of one.
Performance
The advantages of Hyper-Threading are listed as: improved support for multi-threaded code, allowing multiple threads to run simultaneously, improved reaction and response time, and increased number of users a server can support.
According to Intel, the first implementation only used an additional 5% of the die area over the "normal" processor, yet yielded performance improvements of 15–30%.
Intel claims up to a 30% speed improvement compared against an otherwise identical, non-SMT Pentium 4. The performance improvement seen is very application-dependent, however, and some programs actually slow down slightly when Hyper Threading Technology is turned on. This is due to the replay system of the Pentium 4 tying up valuable execution resources, thereby starving the other thread. (The Pentium 4 Prescott core gained a replay queue, which reduces execution time needed for the replay system, but this is not enough to completely overcome the performance hit.) However, any performance degradation is unique to the Pentium 4 (due to various architectural nuances), and is not characteristic of simultaneous multithreading in general.
Hyper-Threading works by duplicating certain sections of the processor—those that store the architectural state—but not duplicating the main execution resources. This allows a Hyper-Threading equipped processor to pretend to be two "logical" processors to the host operating system, allowing the operating system to schedule two threads or processes simultaneously. Where execution resources in a non-Hyper-Threading capable processor are not used by the current task, and especially when the processor is stalled, a Hyper-Threading equipped processor may use those execution resources to execute another scheduled task. (The processor may stall due to a cache miss, branch misprediction, or data dependency.)
Except for its performance implications, this innovation is transparent to operating systems and programs. All that is required to take advantage of Hyper-Threading is symmetric multiprocessing (SMP) support in the operating system, as the logical processors appear as standard separate processors.
However, it is possible to optimize operating system behavior on Hyper-Threading capable systems, such as the Linux techniques discussed in Kernel Traffic. For example, consider an SMP system with two physical processors that are both Hyper-Threaded (for a total of four logical processors). If the operating system's process scheduler is unaware of Hyper-Threading, it would treat all four processors the same. As a result, if only two processes are eligible to run, it might choose to schedule those processes on the two logical processors that happen to belong to one of the physical processors. Thus, one CPU would be extremely busy while the other CPU would be completely idle, leading to poor overall performance. This problem can be avoided by improving the scheduler to treat logical processors differently from physical processors; in a sense, this is a limited form of the scheduler changes that are required for NUMA systems.
Security
In May 2005 Colin Percival presented a paper, Cache Missing for Fun and Profit (PDF file), demonstrating that a malicious thread operating with limited privileges permits monitoring of the execution of another thread, allowing for the possibility of theft of cryptographic keys.
Future
Older Pentium 4 based MPUs use Hyper-Threading, but the current-generation cores, Merom, Conroe and Woodcrest, do not. Hyper-Threading is a specialized form of simultaneous multithreading (SMT), which has been said to be on Intel plans for the generation after Merom, Conroe and Woodcrest.
More recently Hyper-Threading has been branded as energy inefficient. For example, specialist low power CPU design company ARM has stated SMT can use up to 46% more power than dual CPU designs. Furthermore, they claim SMT increases cache thrashing by 42%, whereas dual core results in a 37% decrease[1]. These considerations are claimed to be the reason Intel has dropped SMT from new cores.
However, some low-power chips do still use multithreading, including the PPE from the Cell processor, the CPUs in the Playstation 3, Sun Microsystem's Niagara and the MIPS 34K.
==============
Source: http://en.wikipedia.org/wiki/Hyper-threading
==============
Amd MultiCore, Intel MultiCore
AMD Multicore and Intel Multicore
----------------------------
A multi-core microprocessor is one that combines two or more independent processors into a single package, often a single integrated circuit (IC). A dual-core device contains two independent microprocessors. In general, multi-core microprocessors allow a computing device to exhibit some form of thread-level parallelism (TLP) without including multiple microprocessors in separate physical packages. This form of TLP is often known as chip-level multiprocessing
Terminology
There is some discrepancy in the semantics by which the terms "multi-core" and "dual-core" are defined. Most commonly they are used to refer to some sort of central processing unit (CPU), but are sometimes also applied to DSPs and SoCs. Additionally, some use these terms only to refer to multi-core microprocessors that are manufactured on the same integrated circuit die. These persons generally prefer to refer to separate microprocessor dies in the same package by another name, such as "multi-chip module", "double core", or even "twin core". This article uses both the terms "multi-core" and "dual-core" to reference microelectronic CPUs manufactured on the same integrated circuit, unless otherwise noted.
[edit] Development motivation
While CMOS manufacturing technology continues to improve, reducing the size of single gates, physical limits of semiconductor-based microelectronics become a major design concern. Some effects of these physical limitations can cause significant heat dissipation and data synchronization problems. The demand for more complex and capable microprocessors causes CPU designers to utilize various methods of increasing performance. Some ILP methods like superscalar pipelining are suitable for many applications, but are inefficient for others that tend to contain difficult-to-predict code. Many applications are better suited to TLP methods, and multiple independent CPUs is one common method used to increase a system's overall TLP. A combination of increased available space due to refined manufacturing processes and the demand for increased TLP is the logic behind the creation of multi-core CPUs.
[edit] Commercial incentives
Several business motives drive the development of dual-core architectures. Since SMP designs have been long implemented using discrete CPUs, the issues regarding implementing the architecture and supporting it in software are well known. Additionally, utilizing a proven processing core design (e.g. Freescale's e700 core) without architectural changes reduces design risk significantly. Finally, the connotation of the terminology "dual-core" (and other multiples) lends itself to marketing efforts.
Additionally, for general-purpose processors, much of the motivation for multi-core processors comes from the increasing difficulty of improving processor performance by increasing the operating frequency (frequency-scaling). In order to continue delivering regular performance improvements for general-purpose processors, manufacturers such as Intel and AMD have turned to multi-core designs, sacrificing lower manufacturing costs for higher performance in some applications and systems.
Multi-core architectures are being developed, but so are the alternatives. An especially strong contender for established markets is to integrate more peripheral functions into the chip.
[edit] Advantages
* Proximity of multiple CPU cores on the same die have the advantage that the cache coherency circuitry can operate at a much higher clock rate than is possible if the signals have to travel off-chip, so combining equivalent CPUs on a single die significantly improves the performance of cache snoop (alternative: Bus snooping) operations.[citation needed] In simpler words, it means that because the signal between different chips has to travel a shorter distance, it does not degenerate as much, which allows more data to be sent at the same period of time - as individual signals can be shorter and do not need to be repeated as often.
* Assuming that the die can fit into the package, physically, the multi-core CPU designs require much less Printed Circuit Board (PCB) space than multi-chip SMP designs.
* A dual-core processor uses slightly less power than two coupled single-core processors, principally because of the increased power required to drive signals external to the chip and because the smaller silicon process geometry allows the cores to operate at lower voltages; such reduction reduces latency. Furthermore, the cores share some circuitry, like the L2 cache and the interface to the front side bus (FSB).[citation needed]
* In terms of competing technologies for the available silicon die area, multi-core design can make use of proven CPU core library designs and produce a product with lower risk of design error than devising a new wider core design. Also, adding more cache suffers from diminishing returns.[citation needed]
[edit] Disadvantages
* In addition to operating system (OS) support, adjustments to existing software are required to maximize utilization of the computing resources provided by multi-core processors. Also, the ability of multi-core processors to increase application performance depends on the use of multiple threads within applications. For example, most current (2006) video games will run faster on a 3 GHz single-core processor than on a 2GHz dual-core processor (of the same core architecture), despite the dual-core theoretically having more processing power, because they are incapable of efficiently using more than one core at a time.[1]
* Integration of a multi-core chip drives production yields down and they are more difficult to manage thermally than lower-density single-chip designs.[citation needed]
* From an architectural point of view, ultimately, single CPU designs may make better use of the silicon surface area than multiprocessing cores, so a development commitment to this architecture may carry the risk of obsolescence.[citation needed]
* Raw processing power is not the only constraint on system performance. Two processing cores sharing the same system bus and memory bandwidth limits the real-world performance advantage. If a single core is close to being memory bandwidth limited, going to dual-core might only give 30% to 70% improvement. If memory-bandwidth is not a problem a 90% improvement can be expected. It would be possible for an application that used 2 CPUs to end up running faster on one dual-core if communication between the CPUs was the limiting factor, which would count as more than 100% improvement. [citation needed]
[edit] Hardware trend
* Multi-core to many-core: from dual-, quad-, eight-core to tens or even hundreds of cores.
* Mixed with simultaneous multithreading or hyperthreading
* Heterogeneous: special purpose processors cores in addition to general purpose cores for higher efficiency in processing multimedia, recognition and networking applications
* Energy-efficiency: focus on performance-per-watt with advanced fine-grain or ultra fine-grain power management and dynamic voltage and frequency scaling (DVFS)
* Hardware-assisted platform virtualization
* Memory-on-chip
[edit] Software impact
Software benefits from multicore architectures where code can be executed in parallel. Under most common operating systems this requires code to execute in separate threads. Each application running on a system runs in its own thread so multiple applications will benefit from multicore architectures. Each application may also have multiple threads but, in most cases, it must be specifically written to utilize multiple threads. Operating system software also tends to run many threads as a part of its normal operation. Running virtual machines will benefit from adoption of multiple core architectures since each virtual machine runs independently of others and can be executed in parallel.
Most application software is not written to use multiple concurrent threads intensively because of the challenge of doing so. A frequent pattern in multithreaded application design is where a single thread does the intensive work while other threads do much less. For example a virus scan application may create a new thread for the scan process, while the gui thread waits for commands from the user (e.g. cancel the scan). In such cases, multicore architecture is of little benefit for the application itself due to the single thread doing all heavy lifting and the inability to balance the work evenly across multiple cores. Programming truly multithreaded code often requires complex co-ordination of threads and can easily introduce subtle and difficult to find bugs due to the interleaving of processing on data shared between threads (thread-safety). Debugging such code when it breaks is also much more difficult than single-threaded code. Also there has been a perceived lack of motivation for writing consumer-level threaded applications because of the relative rarity of consumer-level multiprocessor hardware. Although threaded applications incur little additional performance penalty on single-processor machines, the extra overhead of development was difficult to justify due to preponderance of single-processor machines.
As of Fall 2006, with the typical mix of mass-market applications the main benefit to an ordinary user from a multi-core CPU will be improved multitasking performance. In particular, the impact on foreground responsiveness from a CPU-intensive background task (such as running a full system scan with antivirus or other anti-malware utilites) may be reduced.
Given the increasing emphasis on multicore chip design, stemming from the grave thermal and power consumption problems posed by any further significant increase in processor clock speeds, the extent to which software can be multithreaded to take advantage of these new chips is likely to be the single greatest constraint on computer performance in the future. If developers are unable to design software to fully exploit the resources provided by multiple cores, then they will ultimately reach an insurmountable performance ceiling.
Current software titles designed to utilize multi-core technologies include: World of Warcraft, City of Heroes, City of Villains, Maya, Blender3D, Quake 3 & Quake 4, Elder Scrolls: Oblivion (requires editing the .ini file to activate), Falcon 4: Allied Force, 3DS Max, Adobe Photoshop, Paint.NET, Windows XP Professional, Windows 2003, Windows Vista, Mac OS X, Linux, Tangosol Coherence, GigaSpaces EAG, DataRush from Pervasive Software, numerous Ulead products including MediaStudio Pro 7 & 8 (pro video editor), VideoStudio 10 and 10 Plus (consumer video editor), DVD MovieFactory 5 & 5 Plus (DVD authoring) and PhotoImpact 12 (graphics tool), and many operating systems that are streamlined for server use.
Most video games designed to run on Sony's Playstation 3 are expected to take advantage of its 8-core Cell microprocessor. The highly anticipated first-person shooter Resistance: Fall of Man reportedly dedicates a single SPE core of the Cell to enemy AI. How other upcoming PS3 title utilize the hardwares multi-core design is unknown.
Parallel programming techniques can benefit from multiple cores directly. Some existing parallel programming models such as OpenMP and MPI can be used on multi-core platforms. David A. Bader has designed a portable multicore programming methodology called SWARM [2]. Other research efforts have been seen also, like Cray’s Chapel, Sun’s Fortress, and IBM’s X10.
Concurrency acquires a central role in true parallel application. The basic steps in designing parallel applications are:
Partitioning
The partitioning stage of a design is intended to expose opportunities for parallel execution. Hence, the focus is on defining a large number of small tasks in order to yield what is termed a fine-grained decomposition of a problem.
Communication
The tasks generated by a partition are intended to execute concurrently but cannot, in general, execute independently. The computation to be performed in one task will typically require data associated with another task. Data must then be transferred between tasks so as to allow computation to proceed. This information flow is specified in the communication phase of a design.
Agglomeration
In the third stage, we move from the abstract toward the concrete. We revisit decisions made in the partitioning and communication phases with a view to obtaining an algorithm that will execute efficiently on some class of parallel computer. In particular, we consider whether it is useful to combine, or agglomerate, tasks identified by the partitioning phase, so as to provide a smaller number of tasks, each of greater size. We also determine whether it is worthwhile to replicate data and/or computation.
Mapping
In the fourth and final stage of the parallel algorithm design process, we specify where each task is to execute. This mapping problem does not arise on uniprocessors or on shared-memory computers that provide automatic task scheduling.
On the other hand, on the server side, multicore processors are ideal because they allow many users to connect to a site simultaneously and have independent threads of execution. This allows for Web servers and application servers that have much better throughput.
[edit] Licensing
Another issue is the question of software licensing for multi-core CPUs. Typically enterprise server software is licensed "per processor". In the past a CPU was a processor (and moreover most computers had only one CPU) and there was no ambiguity. Now there is the possibility of counting cores as processors and charging a customer for two licenses when they use a dual-core CPU. However, the trend seems to be counting dual-core chips as a single processor as Microsoft, Intel, and AMD support this view. Oracle counts AMD and Intel dual-core CPUs as a single processor but has other numbers for other types. IBM, HP and Microsoft count a multi-chip module as multiple processors. If multi-chip modules counted as one processor then CPU makers would have an incentive to make large expensive multi-chip modules so their customers saved on software licensing. So it seems that the industry is slowly heading towards counting each die (see Integrated circuit) as a processor, no matter how many cores each die has. Intel has released Paxville which is really a multi-chip module but Intel is calling it a dual-core. It is not clear yet how licensing will work for Paxville. This is an unresolved and thorny issue for software companies and customers.
[edit] Commercial examples
* International Business Machines (IBM)'s POWER4, first Dual-Core module processor released in 2000.
* IBM's POWER5 dual-core chip is now in production, and the company has a PowerPC 970MP dual-core processor in production that was used in the Apple Power Mac G5.
* Cradle Technologies multi-core DSP processor (CT3400, CT3600)
* Broadcom SiByte (SB1250, SB1255, SB1455)
* PA-RISC (PA-8800)
* Sun Microsystems
o UltraSPARC IV,
o UltraSPARC IV+,
o UltraSPARC T1 eight cores, 32 threads
* AMD released its dual-core Opteron server/workstation processors on 22 April 2005, and its dual-core desktop processors, the Athlon 64 X2 family, were released on 31 May 2005. AMD have also recently released the FX-60, FX-62 and FX-64 for high performance desktops, and Turion 64 X2 for laptops.
* Intel is currently shipping Core Duo, Core 2 Duo, and Xeon (x1xx series) microprocessors with dual-core technology. These chips, based on the Pentium M (Core Duo) and Core (Core 2 Duo and Xeon) replaced the earlier Pentium D chips, which were based on the Pentium 4. Intel also markets quad-core versions of the Core 2 chip, called the Core 2 Quad and Core 2 Extreme.
* Motorola/Freescale has dual-core ICs based on the PowerPC e500 core, and e600 and e700 cores in development.
* Microsoft's Xbox 360 game console uses a triple core PowerPC microprocessor.
* The Cell processor used in the PlayStation 3 has a 9 core design, although in the PS3 only 8 cores are enabled.
* Raza Microelectronics' XLR processor has eight MIPS cores.
* Cavium Networks' Octeon processor has 16 MIPS cores.
* Commendo Voyager software service is a multi-core design running on Intel dual-core processors.
* ARM MPCore is a fully synthesizable multicore container for ARM9 and ARM11 processor cores, intended for high-performance embedded and entertainment applications.
* Intel has developed an 80-core processor prototype that has each core running at 3.16GHz, which it says will be released within the next five years.[1]
* The Parallax Propeller is a cheap and simple multiprocessing microcontroller with eight 32 bit cores controlled by an internal bus controller. It uses the proprietary Spin computer language.
Quad-core processors are announced by Intel[2] to be produced in 2006 and AMD[3] for 2007.
[edit] Notes
1. ↑ Digital signal processors, DSPs, have utilized dual-core architectures for much longer than high-end general purpose processors. A typical example of a DSP-specific implementation would be a combination of a RISC CPU and a DSP MPU. This allows for the design of products that require a general purpose processor for user interfaces and a DSP for real-time data processing; this type of design is suited to e.g. mobile phones.
2. ↑ Two types of operating systems are able to utilize a dual-CPU multiprocessor: partitioned multiprocessing and symmetric multiprocessing (SMP). In a partitioned architecture, each CPU boots into separate segments of physical memory and operate independently; in an SMP OS, processors work in a shared space, executing threads within the OS independently.
=========================
Source: http://en.wikipedia.org/wiki/Multi-core_(computing)
=========================
Friday, December 22, 2006
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Soltia pe care o au in vedere autoritatile de la Madrid prevede ca, in primii doi ani dupa aderare, accesul muncitorilor romani sa se faca pe baza de permis de munca si de viza de munca. La finalul primului an se va face o evaluare, in urma careia este posibila ridicarea acestor restrictii.
asta era o stire care amu mi'o venit in email... (o parte din ea)...
nici nu stiti cat ma abtin sa nu injur...
Mama lor de Spanioli, au uitat toti cine a ramas in Europa si cine a trecut oceanul mai ales motivele ptr care au trecut, majoritatea Spanioli... wink.gif nu numai ca erau fomisti rau plecand dupa ceva aur in America dar majoritatea erau vai de mama lor, hoti, criminali, urmariti de justitie, oameni fara scrupule, etc... de unde credeti ca sunt Americanii ? ... va mai amintiti filmele western si actiunea lor... da alea erau inspirate din realitate, un popor inascut sa ucida ptr pamant, ptr femei, ptr orice... nu avea importanta, se impuscau ca'n codru! Cine erau respectivii ? Pai ia ghiciti ? (ca din alta galaxie nu au ajuns acolo).
Ca sa nu amintesc ca au exterminat cat sa putut de mult din ce se ne numeau "pielie rosii". Pentru ce ? Pamant, aur, etc!!!
Pana la urma ca tot veni vorba SUA sau America: acea tara este cladita si ridicata prin sange si sclavi ! Azi poate ca lucrurle stau altfel, dar istoria e istorie, iar in istoria nostra nu am auzit de asa ispravi ca la Americani! ... Cine nu a vazut file western sa citeasca Karl May, cartile sunt cu mult peste filme !
... si Sclavia ? Or fi fost ei si la noi Boieri sau ce a mai fost, dar sclavie ca'n America nu a fost!
Sunday, December 17, 2006
de ieri am un alt blog :) da...
asta: http://www.roportal.ro/discutii/blog/byrev
--------
this is my new blog: http://www.roportal.ro/discutii/blog/byrev/
======================
Si nu uitati: Avatars Gallery:
======================
asta: http://www.roportal.ro/discutii/blog/byrev
--------
this is my new blog: http://www.roportal.ro/discutii/blog/byrev/
======================
Si nu uitati: Avatars Gallery:
======================
Wednesday, December 13, 2006
Posturi sterese din BLOG de catre admini de la SOFTPEDIA
Unde sa mai pomenit sa ai un blog, sa'ti pui propriile linkuri in el, sa postezi ce te doare si ce doresti tu atata timp cat ceea ce este acolo nu este ilegal, si sa vina un admin de pe siteul respectiv sa'ti stearga propriile posturi !?
Unde sa mai pomenit asta , E doar blogul tau !!! Adica ceea ce pui acolo te priveste, iar vizitatorii nu'i stirigi in gura mare, vin singuri pentru ca gasesc ceea ce cauta la tine in blog!!!
Acest lucru mi sa intamplat mie pe softpedia... asta este blogul: Porn
si dupa ce am pus vre'o 10 posturi unele dintre ele intradevar cu reclama la Avatars Galery, ma pomenesc ca'mi sterge un admin care sa sculat prea de dimineata si a zis hai sa facem varza pe aici ... si mi-a ras toate posturile... ma toate !!! Cacamasi pe ele... pai ce avea mancatiasi ca dor nu era reclama pe usa lui de la apartament... cica facem reclama la nush ce site... ;)) lol
pai io i'am si vazut feedback linkul in sietul meu cand a intrat !!! cica pe nush ce site !!! hahaha!!!
deci concluzia... alegi alt blog, pe softpedia sunteti cu posturile la discretia lor.. si te pomenetsi ca'ti sterg jumatate din posturi pentru ca nu le plac negrii, ungurii, tiganii, reclama... p'la mea... da ce trebuie sa puenm frate acolo !?? Retete cu carnati de Craciun sa le citesca bunica la aragaz? !
sa ne auzium cubine!
Unde sa mai pomenit asta , E doar blogul tau !!! Adica ceea ce pui acolo te priveste, iar vizitatorii nu'i stirigi in gura mare, vin singuri pentru ca gasesc ceea ce cauta la tine in blog!!!
Acest lucru mi sa intamplat mie pe softpedia... asta este blogul: Porn
si dupa ce am pus vre'o 10 posturi unele dintre ele intradevar cu reclama la Avatars Galery, ma pomenesc ca'mi sterge un admin care sa sculat prea de dimineata si a zis hai sa facem varza pe aici ... si mi-a ras toate posturile... ma toate !!! Cacamasi pe ele... pai ce avea mancatiasi ca dor nu era reclama pe usa lui de la apartament... cica facem reclama la nush ce site... ;)) lol
pai io i'am si vazut feedback linkul in sietul meu cand a intrat !!! cica pe nush ce site !!! hahaha!!!
deci concluzia... alegi alt blog, pe softpedia sunteti cu posturile la discretia lor.. si te pomenetsi ca'ti sterg jumatate din posturi pentru ca nu le plac negrii, ungurii, tiganii, reclama... p'la mea... da ce trebuie sa puenm frate acolo !?? Retete cu carnati de Craciun sa le citesca bunica la aragaz? !
sa ne auzium cubine!
Tuesday, December 12, 2006
Adriana Bahmuteanu
Corect este : Adriana Bahmuteanu = Bagabela, Putoret, Gagicareala (asa zice la dimineatza dementa, caterinca cu ... zice ici: ByREV Blog-u
News:
Dynamic Feedback LINK!
12 12 2006
Vreti sa vedeti ce este ala ? Aici : Avatars Galery
Ce inseamna ? Pai e simpla ideea: Atata timp cat exista vizitatori de pe site’ul X pe siteul Y atata timp siteul Y asigura un Back Link pe o pagina dedicata acestui scop ! Deci ideea este simpla dar nu chiar extrem de simpla. FeedBack Linkul este garantat doar ptr o singura zi… daca in urmatoarea zi nu mai exista vizite...
read the rest here : http://byrev.blog-u.net/?p=190
Dynamic Feedback LINK!
12 12 2006
Vreti sa vedeti ce este ala ? Aici : Avatars Galery
Ce inseamna ? Pai e simpla ideea: Atata timp cat exista vizitatori de pe site’ul X pe siteul Y atata timp siteul Y asigura un Back Link pe o pagina dedicata acestui scop ! Deci ideea este simpla dar nu chiar extrem de simpla. FeedBack Linkul este garantat doar ptr o singura zi… daca in urmatoarea zi nu mai exista vizite...
read the rest here : http://byrev.blog-u.net/?p=190
Monday, December 11, 2006
Thursday, December 7, 2006
Imperia Network!
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