Amd MultiCore, Intel MultiCore

AMD Multicore and Intel Multicore
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A multi-core microprocessor is one that combines two or more independent processors into a single package, often a single integrated circuit (IC). A dual-core device contains two independent microprocessors. In general, multi-core microprocessors allow a computing device to exhibit some form of thread-level parallelism (TLP) without including multiple microprocessors in separate physical packages. This form of TLP is often known as chip-level multiprocessing

Terminology

There is some discrepancy in the semantics by which the terms "multi-core" and "dual-core" are defined. Most commonly they are used to refer to some sort of central processing unit (CPU), but are sometimes also applied to DSPs and SoCs. Additionally, some use these terms only to refer to multi-core microprocessors that are manufactured on the same integrated circuit die. These persons generally prefer to refer to separate microprocessor dies in the same package by another name, such as "multi-chip module", "double core", or even "twin core". This article uses both the terms "multi-core" and "dual-core" to reference microelectronic CPUs manufactured on the same integrated circuit, unless otherwise noted.

[edit] Development motivation

While CMOS manufacturing technology continues to improve, reducing the size of single gates, physical limits of semiconductor-based microelectronics become a major design concern. Some effects of these physical limitations can cause significant heat dissipation and data synchronization problems. The demand for more complex and capable microprocessors causes CPU designers to utilize various methods of increasing performance. Some ILP methods like superscalar pipelining are suitable for many applications, but are inefficient for others that tend to contain difficult-to-predict code. Many applications are better suited to TLP methods, and multiple independent CPUs is one common method used to increase a system's overall TLP. A combination of increased available space due to refined manufacturing processes and the demand for increased TLP is the logic behind the creation of multi-core CPUs.

[edit] Commercial incentives

Several business motives drive the development of dual-core architectures. Since SMP designs have been long implemented using discrete CPUs, the issues regarding implementing the architecture and supporting it in software are well known. Additionally, utilizing a proven processing core design (e.g. Freescale's e700 core) without architectural changes reduces design risk significantly. Finally, the connotation of the terminology "dual-core" (and other multiples) lends itself to marketing efforts.

Additionally, for general-purpose processors, much of the motivation for multi-core processors comes from the increasing difficulty of improving processor performance by increasing the operating frequency (frequency-scaling). In order to continue delivering regular performance improvements for general-purpose processors, manufacturers such as Intel and AMD have turned to multi-core designs, sacrificing lower manufacturing costs for higher performance in some applications and systems.

Multi-core architectures are being developed, but so are the alternatives. An especially strong contender for established markets is to integrate more peripheral functions into the chip.

[edit] Advantages

* Proximity of multiple CPU cores on the same die have the advantage that the cache coherency circuitry can operate at a much higher clock rate than is possible if the signals have to travel off-chip, so combining equivalent CPUs on a single die significantly improves the performance of cache snoop (alternative: Bus snooping) operations.[citation needed] In simpler words, it means that because the signal between different chips has to travel a shorter distance, it does not degenerate as much, which allows more data to be sent at the same period of time - as individual signals can be shorter and do not need to be repeated as often.
* Assuming that the die can fit into the package, physically, the multi-core CPU designs require much less Printed Circuit Board (PCB) space than multi-chip SMP designs.
* A dual-core processor uses slightly less power than two coupled single-core processors, principally because of the increased power required to drive signals external to the chip and because the smaller silicon process geometry allows the cores to operate at lower voltages; such reduction reduces latency. Furthermore, the cores share some circuitry, like the L2 cache and the interface to the front side bus (FSB).[citation needed]
* In terms of competing technologies for the available silicon die area, multi-core design can make use of proven CPU core library designs and produce a product with lower risk of design error than devising a new wider core design. Also, adding more cache suffers from diminishing returns.[citation needed]

[edit] Disadvantages

* In addition to operating system (OS) support, adjustments to existing software are required to maximize utilization of the computing resources provided by multi-core processors. Also, the ability of multi-core processors to increase application performance depends on the use of multiple threads within applications. For example, most current (2006) video games will run faster on a 3 GHz single-core processor than on a 2GHz dual-core processor (of the same core architecture), despite the dual-core theoretically having more processing power, because they are incapable of efficiently using more than one core at a time.[1]
* Integration of a multi-core chip drives production yields down and they are more difficult to manage thermally than lower-density single-chip designs.[citation needed]
* From an architectural point of view, ultimately, single CPU designs may make better use of the silicon surface area than multiprocessing cores, so a development commitment to this architecture may carry the risk of obsolescence.[citation needed]
* Raw processing power is not the only constraint on system performance. Two processing cores sharing the same system bus and memory bandwidth limits the real-world performance advantage. If a single core is close to being memory bandwidth limited, going to dual-core might only give 30% to 70% improvement. If memory-bandwidth is not a problem a 90% improvement can be expected. It would be possible for an application that used 2 CPUs to end up running faster on one dual-core if communication between the CPUs was the limiting factor, which would count as more than 100% improvement. [citation needed]

[edit] Hardware trend

* Multi-core to many-core: from dual-, quad-, eight-core to tens or even hundreds of cores.
* Mixed with simultaneous multithreading or hyperthreading
* Heterogeneous: special purpose processors cores in addition to general purpose cores for higher efficiency in processing multimedia, recognition and networking applications
* Energy-efficiency: focus on performance-per-watt with advanced fine-grain or ultra fine-grain power management and dynamic voltage and frequency scaling (DVFS)
* Hardware-assisted platform virtualization
* Memory-on-chip

[edit] Software impact

Software benefits from multicore architectures where code can be executed in parallel. Under most common operating systems this requires code to execute in separate threads. Each application running on a system runs in its own thread so multiple applications will benefit from multicore architectures. Each application may also have multiple threads but, in most cases, it must be specifically written to utilize multiple threads. Operating system software also tends to run many threads as a part of its normal operation. Running virtual machines will benefit from adoption of multiple core architectures since each virtual machine runs independently of others and can be executed in parallel.

Most application software is not written to use multiple concurrent threads intensively because of the challenge of doing so. A frequent pattern in multithreaded application design is where a single thread does the intensive work while other threads do much less. For example a virus scan application may create a new thread for the scan process, while the gui thread waits for commands from the user (e.g. cancel the scan). In such cases, multicore architecture is of little benefit for the application itself due to the single thread doing all heavy lifting and the inability to balance the work evenly across multiple cores. Programming truly multithreaded code often requires complex co-ordination of threads and can easily introduce subtle and difficult to find bugs due to the interleaving of processing on data shared between threads (thread-safety). Debugging such code when it breaks is also much more difficult than single-threaded code. Also there has been a perceived lack of motivation for writing consumer-level threaded applications because of the relative rarity of consumer-level multiprocessor hardware. Although threaded applications incur little additional performance penalty on single-processor machines, the extra overhead of development was difficult to justify due to preponderance of single-processor machines.

As of Fall 2006, with the typical mix of mass-market applications the main benefit to an ordinary user from a multi-core CPU will be improved multitasking performance. In particular, the impact on foreground responsiveness from a CPU-intensive background task (such as running a full system scan with antivirus or other anti-malware utilites) may be reduced.

Given the increasing emphasis on multicore chip design, stemming from the grave thermal and power consumption problems posed by any further significant increase in processor clock speeds, the extent to which software can be multithreaded to take advantage of these new chips is likely to be the single greatest constraint on computer performance in the future. If developers are unable to design software to fully exploit the resources provided by multiple cores, then they will ultimately reach an insurmountable performance ceiling.

Current software titles designed to utilize multi-core technologies include: World of Warcraft, City of Heroes, City of Villains, Maya, Blender3D, Quake 3 & Quake 4, Elder Scrolls: Oblivion (requires editing the .ini file to activate), Falcon 4: Allied Force, 3DS Max, Adobe Photoshop, Paint.NET, Windows XP Professional, Windows 2003, Windows Vista, Mac OS X, Linux, Tangosol Coherence, GigaSpaces EAG, DataRush from Pervasive Software, numerous Ulead products including MediaStudio Pro 7 & 8 (pro video editor), VideoStudio 10 and 10 Plus (consumer video editor), DVD MovieFactory 5 & 5 Plus (DVD authoring) and PhotoImpact 12 (graphics tool), and many operating systems that are streamlined for server use.

Most video games designed to run on Sony's Playstation 3 are expected to take advantage of its 8-core Cell microprocessor. The highly anticipated first-person shooter Resistance: Fall of Man reportedly dedicates a single SPE core of the Cell to enemy AI. How other upcoming PS3 title utilize the hardwares multi-core design is unknown.

Parallel programming techniques can benefit from multiple cores directly. Some existing parallel programming models such as OpenMP and MPI can be used on multi-core platforms. David A. Bader has designed a portable multicore programming methodology called SWARM [2]. Other research efforts have been seen also, like Cray’s Chapel, Sun’s Fortress, and IBM’s X10.

Concurrency acquires a central role in true parallel application. The basic steps in designing parallel applications are:

Partitioning
The partitioning stage of a design is intended to expose opportunities for parallel execution. Hence, the focus is on defining a large number of small tasks in order to yield what is termed a fine-grained decomposition of a problem.

Communication
The tasks generated by a partition are intended to execute concurrently but cannot, in general, execute independently. The computation to be performed in one task will typically require data associated with another task. Data must then be transferred between tasks so as to allow computation to proceed. This information flow is specified in the communication phase of a design.

Agglomeration
In the third stage, we move from the abstract toward the concrete. We revisit decisions made in the partitioning and communication phases with a view to obtaining an algorithm that will execute efficiently on some class of parallel computer. In particular, we consider whether it is useful to combine, or agglomerate, tasks identified by the partitioning phase, so as to provide a smaller number of tasks, each of greater size. We also determine whether it is worthwhile to replicate data and/or computation.

Mapping
In the fourth and final stage of the parallel algorithm design process, we specify where each task is to execute. This mapping problem does not arise on uniprocessors or on shared-memory computers that provide automatic task scheduling.

On the other hand, on the server side, multicore processors are ideal because they allow many users to connect to a site simultaneously and have independent threads of execution. This allows for Web servers and application servers that have much better throughput.

[edit] Licensing

Another issue is the question of software licensing for multi-core CPUs. Typically enterprise server software is licensed "per processor". In the past a CPU was a processor (and moreover most computers had only one CPU) and there was no ambiguity. Now there is the possibility of counting cores as processors and charging a customer for two licenses when they use a dual-core CPU. However, the trend seems to be counting dual-core chips as a single processor as Microsoft, Intel, and AMD support this view. Oracle counts AMD and Intel dual-core CPUs as a single processor but has other numbers for other types. IBM, HP and Microsoft count a multi-chip module as multiple processors. If multi-chip modules counted as one processor then CPU makers would have an incentive to make large expensive multi-chip modules so their customers saved on software licensing. So it seems that the industry is slowly heading towards counting each die (see Integrated circuit) as a processor, no matter how many cores each die has. Intel has released Paxville which is really a multi-chip module but Intel is calling it a dual-core. It is not clear yet how licensing will work for Paxville. This is an unresolved and thorny issue for software companies and customers.

[edit] Commercial examples

* International Business Machines (IBM)'s POWER4, first Dual-Core module processor released in 2000.
* IBM's POWER5 dual-core chip is now in production, and the company has a PowerPC 970MP dual-core processor in production that was used in the Apple Power Mac G5.
* Cradle Technologies multi-core DSP processor (CT3400, CT3600)
* Broadcom SiByte (SB1250, SB1255, SB1455)
* PA-RISC (PA-8800)
* Sun Microsystems
o UltraSPARC IV,
o UltraSPARC IV+,
o UltraSPARC T1 eight cores, 32 threads
* AMD released its dual-core Opteron server/workstation processors on 22 April 2005, and its dual-core desktop processors, the Athlon 64 X2 family, were released on 31 May 2005. AMD have also recently released the FX-60, FX-62 and FX-64 for high performance desktops, and Turion 64 X2 for laptops.
* Intel is currently shipping Core Duo, Core 2 Duo, and Xeon (x1xx series) microprocessors with dual-core technology. These chips, based on the Pentium M (Core Duo) and Core (Core 2 Duo and Xeon) replaced the earlier Pentium D chips, which were based on the Pentium 4. Intel also markets quad-core versions of the Core 2 chip, called the Core 2 Quad and Core 2 Extreme.
* Motorola/Freescale has dual-core ICs based on the PowerPC e500 core, and e600 and e700 cores in development.
* Microsoft's Xbox 360 game console uses a triple core PowerPC microprocessor.
* The Cell processor used in the PlayStation 3 has a 9 core design, although in the PS3 only 8 cores are enabled.
* Raza Microelectronics' XLR processor has eight MIPS cores.
* Cavium Networks' Octeon processor has 16 MIPS cores.
* Commendo Voyager software service is a multi-core design running on Intel dual-core processors.
* ARM MPCore is a fully synthesizable multicore container for ARM9 and ARM11 processor cores, intended for high-performance embedded and entertainment applications.
* Intel has developed an 80-core processor prototype that has each core running at 3.16GHz, which it says will be released within the next five years.[1]
* The Parallax Propeller is a cheap and simple multiprocessing microcontroller with eight 32 bit cores controlled by an internal bus controller. It uses the proprietary Spin computer language.

Quad-core processors are announced by Intel[2] to be produced in 2006 and AMD[3] for 2007.

[edit] Notes

1. ↑ Digital signal processors, DSPs, have utilized dual-core architectures for much longer than high-end general purpose processors. A typical example of a DSP-specific implementation would be a combination of a RISC CPU and a DSP MPU. This allows for the design of products that require a general purpose processor for user interfaces and a DSP for real-time data processing; this type of design is suited to e.g. mobile phones.
2. ↑ Two types of operating systems are able to utilize a dual-CPU multiprocessor: partitioned multiprocessing and symmetric multiprocessing (SMP). In a partitioned architecture, each CPU boots into separate segments of physical memory and operate independently; in an SMP OS, processors work in a shared space, executing threads within the OS independently.


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Source: http://en.wikipedia.org/wiki/Multi-core_(computing)
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